Re: [Intel-gfx] [PATCH 3/5] drm/i915: WA for zero memory channel

2021-05-24 Thread Clint Taylor
On 5/24/21 2:48 PM, José Roberto de Souza wrote: Commit c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on ICL") assumes that we always have a non-zero dram_info->channels and uses it as a divisor. We need num memory channels to be at least 1 for sane bw limits checking, even

[Intel-gfx] [PATCH 3/5] drm/i915: WA for zero memory channel

2021-05-24 Thread José Roberto de Souza
Commit c457d9cf256e ("drm/i915: Make sure we have enough memory bandwidth on ICL") assumes that we always have a non-zero dram_info->channels and uses it as a divisor. We need num memory channels to be at least 1 for sane bw limits checking, even when PCode returns 0 or there is a error reading it,