Re: [Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

2018-08-17 Thread Rodrigo Vivi
On Thu, Jul 26, 2018 at 07:44:08PM +0530, Mahesh Kumar wrote: > Memory with 16GB dimms require an increase of 1us in level-0 latency. > This patch implements the same. > Bspec: 4381 > > changes since V1: > - s/memdev_info/dram_info > - make skl_is_16gb_dimm pure function > > Signed-off-by: Mahe

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

2018-07-31 Thread Kumar, Mahesh
Hi, On 7/28/2018 11:18 AM, Rodrigo Vivi wrote: On Fri, Jul 27, 2018 at 11:40:14AM +0530, Kumar, Mahesh wrote: Hi Matt, On 7/27/2018 9:21 AM, Matt Turner wrote: On Thu, Jul 26, 2018 at 7:14 AM, Mahesh Kumar wrote: Bspec: 4381 Do we know that these numbers are stable? yes these numbers ar

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

2018-07-27 Thread Rodrigo Vivi
On Fri, Jul 27, 2018 at 11:40:14AM +0530, Kumar, Mahesh wrote: > Hi Matt, > > > On 7/27/2018 9:21 AM, Matt Turner wrote: > > On Thu, Jul 26, 2018 at 7:14 AM, Mahesh Kumar > > wrote: > > > Bspec: 4381 > > Do we know that these numbers are stable? > yes these numbers are fixed in Bspec > > I don'

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

2018-07-26 Thread Kumar, Mahesh
Hi Matt, On 7/27/2018 9:21 AM, Matt Turner wrote: On Thu, Jul 26, 2018 at 7:14 AM, Mahesh Kumar wrote: Bspec: 4381 Do we know that these numbers are stable? yes these numbers are fixed in Bspec I don't know if this form is common in the kernel, but in Mesa we specify the name of the page w

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

2018-07-26 Thread Matt Turner
On Thu, Jul 26, 2018 at 7:14 AM, Mahesh Kumar wrote: > Bspec: 4381 Do we know that these numbers are stable? I don't know if this form is common in the kernel, but in Mesa we specify the name of the page which should always allow readers to find it. __

[Intel-gfx] [PATCH 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

2018-07-26 Thread Mahesh Kumar
Memory with 16GB dimms require an increase of 1us in level-0 latency. This patch implements the same. Bspec: 4381 changes since V1: - s/memdev_info/dram_info - make skl_is_16gb_dimm pure function Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/i915_drv.c | 40