Re: [Intel-gfx] [PATCH 3/4] drm/i915/tgl: Gen12 csb support

2019-07-31 Thread Daniele Ceraolo Spurio
On 7/31/19 12:33 AM, Chris Wilson wrote: Quoting Daniele Ceraolo Spurio (2019-07-31 01:49:01) @@ -1401,7 +1453,7 @@ static void process_csb(struct intel_engine_cs *engine) engine->name, head, buf[2 * head + 0], buf[2 * head + 1]); -

Re: [Intel-gfx] [PATCH 3/4] drm/i915/tgl: Gen12 csb support

2019-07-31 Thread Daniele Ceraolo Spurio
On 7/30/19 11:29 PM, Tvrtko Ursulin wrote: On 31/07/2019 01:49, Daniele Ceraolo Spurio wrote: The CSB format has been reworked for Gen12 to include information on both the context we're switching away from and the context we're switching to. After the change, some of the events don't have the

Re: [Intel-gfx] [PATCH 3/4] drm/i915/tgl: Gen12 csb support

2019-07-31 Thread Chris Wilson
Quoting Daniele Ceraolo Spurio (2019-07-31 01:49:01) > @@ -1401,7 +1453,7 @@ static void process_csb(struct intel_engine_cs *engine) > engine->name, head, > buf[2 * head + 0], buf[2 * head + 1]); > > - switch (csb_parse(execlists,

Re: [Intel-gfx] [PATCH 3/4] drm/i915/tgl: Gen12 csb support

2019-07-30 Thread Tvrtko Ursulin
On 31/07/2019 01:49, Daniele Ceraolo Spurio wrote: The CSB format has been reworked for Gen12 to include information on both the context we're switching away from and the context we're switching to. After the change, some of the events don't have their own bit anymore and need to be inferred fro

[Intel-gfx] [PATCH 3/4] drm/i915/tgl: Gen12 csb support

2019-07-30 Thread Daniele Ceraolo Spurio
The CSB format has been reworked for Gen12 to include information on both the context we're switching away from and the context we're switching to. After the change, some of the events don't have their own bit anymore and need to be inferred from other values in the csb. One of the context IDs (0x7