[Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

2011-10-11 Thread Daniel Vetter
From: Jesse Barnes Signed-off-by: Jesse Barnes Signed-off-by: Kenneth Graunke [danvet: this seems to fix cairo-perf-trace hangs on my snb] Signed-Off-by: Daniel Vetter --- drivers/gpu/drm/i915/i915_reg.h |5 + drivers/gpu/drm/i915/intel_ringbuffer.c | 136

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

2011-10-06 Thread Ben Widawsky
On Thu, Oct 06, 2011 at 11:00:18AM -0700, Eric Anholt wrote: > On Thu, 6 Oct 2011 05:15:23 +, Ben Widawsky wrote: > Non-text part: multipart/signed > > On Wed, Oct 05, 2011 at 05:59:31PM -0700, Eric Anholt wrote: > > > On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky wrote: > > > > I think we

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

2011-10-06 Thread Eric Anholt
On Thu, 6 Oct 2011 05:15:23 +, Ben Widawsky wrote: Non-text part: multipart/signed > On Wed, Oct 05, 2011 at 05:59:31PM -0700, Eric Anholt wrote: > > On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky wrote: > > > I think we also want a TLB invalidate here, bit 18. This requires another > > > w

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

2011-10-05 Thread Ben Widawsky
On Wed, Oct 05, 2011 at 05:59:31PM -0700, Eric Anholt wrote: > On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky wrote: > > I think we also want a TLB invalidate here, bit 18. This requires another > > workaround before issuing this flush: We need 2 Store Data Commands (such as > > MI_STORE_DATA_IM

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

2011-10-05 Thread Eric Anholt
On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky wrote: > I think we also want a TLB invalidate here, bit 18. This requires another > workaround before issuing this flush: We need 2 Store Data Commands (such as > MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) before sending PIPE_CONTROL w/ stall > (20)

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

2011-10-05 Thread Daniel Vetter
On Thu, Oct 06, 2011 at 12:36:03AM +0100, Chris Wilson wrote: > On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky wrote: > > I think we also want a TLB invalidate here, bit 18. This requires another > > workaround before issuing this flush: We need 2 Store Data Commands (such as > > MI_STORE_DATA_I

[Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

2011-10-05 Thread Ben Widawsky
From: Jesse Barnes Signed-off-by: Jesse Barnes Signed-off-by: Kenneth Graunke Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_reg.h |6 ++ drivers/gpu/drm/i915/intel_ringbuffer.c | 148 --- drivers/gpu/drm/i915/intel_ringbuffer.h |1 + 3

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

2011-10-05 Thread Chris Wilson
On Wed, 5 Oct 2011 15:57:13 -0700, Ben Widawsky wrote: > I think we also want a TLB invalidate here, bit 18. This requires another > workaround before issuing this flush: We need 2 Store Data Commands (such as > MI_STORE_DATA_IMM or MI_STORE_DATA_INDEX) before sending PIPE_CONTROL w/ stall > (20)

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

2011-10-05 Thread Ben Widawsky
On Mon, 3 Oct 2011 23:02:40 -0700 Kenneth Graunke wrote: > From: Jesse Barnes > > Signed-off-by: Jesse Barnes > Signed-off-by: Kenneth Graunke > --- > drivers/gpu/drm/i915/i915_reg.h |5 + > drivers/gpu/drm/i915/intel_ringbuffer.c | 136 > --- > 2 f

[Intel-gfx] [PATCH 3/3] drm/i915: Use PIPE_CONTROL for flushing on gen6+.

2011-10-03 Thread Kenneth Graunke
From: Jesse Barnes Signed-off-by: Jesse Barnes Signed-off-by: Kenneth Graunke --- drivers/gpu/drm/i915/i915_reg.h |5 + drivers/gpu/drm/i915/intel_ringbuffer.c | 136 --- 2 files changed, 129 insertions(+), 12 deletions(-) v2: - Add State & Constant C