[Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround

From: Chris Wilson VT-d may cause overfetch of the scanout PTE, both before and after the vma (depending on the scanout orientation). bspec recommends that we provide a tile-row in either directions, and suggests using 168 PTE, warning that the accesses will wrap around the ends of the GGTT. Curr

[Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround

From: Chris Wilson VT-d may cause overfetch of the scanout PTE, both before and after the vma (depending on the scanout orientation). bspec recommends that we provide a tile-row in either directions, and suggests using 168 PTE, warning that the accesses will wrap around the ends of the GGTT. Curr

[Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround

From: Chris Wilson VT-d may cause overfetch of the scanout PTE, both before and after the vma (depending on the scanout orientation). bspec recommends that we provide a tile-row in either directions, and suggests using 168 PTE, warning that the accesses will wrap around the ends of the GGTT. Curr

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround

On Mon, 15 Feb 2021 at 15:56, Chris Wilson wrote: > > VT-d may cause overfetch of the scanout PTE, both before and after the > vma (depending on the scanout orientation). bspec recommends that we > provide a tile-row in either directions, and suggests using 160 PTE, > warning that the accesses wil

[Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround

VT-d may cause overfetch of the scanout PTE, both before and after the vma (depending on the scanout orientation). bspec recommends that we provide a tile-row in either directions, and suggests using 160 PTE, warning that the accesses will wrap around the ends of the GGTT. Currently, we fill the en

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround

On Fri, 12 Feb 2021 at 10:22, Chris Wilson wrote: > > VT-d may cause overfetch of the scanout PTE, both before and after the > vma (depending on the scanout orientation). bspec recommends that we > provide a tile-row in either directions, and suggests using 160 PTE, > warning that the accesses wil

[Intel-gfx] [PATCH 3/3] drm/i915: Refine VT-d scanout workaround

VT-d may cause overfetch of the scanout PTE, both before and after the vma (depending on the scanout orientation). bspec recommends that we provide a tile-row in either directions, and suggests using 160 PTE, warning that the accesses will wrap around the ends of the GGTT. Currently, we fill the en