Re: [Intel-gfx] [PATCH 3/3] drm/i915: HSW FBC WaFbcDisableDpfcClockGating

2013-04-10 Thread Ville Syrjälä
On Tue, Apr 09, 2013 at 03:05:10PM -0300, Rodrigo Vivi wrote: > On Tue, Apr 9, 2013 at 5:37 AM, Ville Syrjälä > wrote: > > > On Mon, Apr 08, 2013 at 06:49:44PM -0300, Rodrigo Vivi wrote: > > > Display register 46500h bit 23 must be set to 1b for the entire time that > > > Frame Buffer Compression

Re: [Intel-gfx] [PATCH 3/3] drm/i915: HSW FBC WaFbcDisableDpfcClockGating

2013-04-09 Thread Rodrigo Vivi
On Tue, Apr 9, 2013 at 5:37 AM, Ville Syrjälä wrote: > On Mon, Apr 08, 2013 at 06:49:44PM -0300, Rodrigo Vivi wrote: > > Display register 46500h bit 23 must be set to 1b for the entire time that > > Frame Buffer Compression is enabled. > > So should we enable it again after FBC is disabled to avo

Re: [Intel-gfx] [PATCH 3/3] drm/i915: HSW FBC WaFbcDisableDpfcClockGating

2013-04-09 Thread Ville Syrjälä
On Mon, Apr 08, 2013 at 06:49:44PM -0300, Rodrigo Vivi wrote: > Display register 46500h bit 23 must be set to 1b for the entire time that > Frame Buffer Compression is enabled. So should we enable it again after FBC is disabled to avoid wasting power? > > Signed-off-by: Rodrigo Vivi > --- > dr

[Intel-gfx] [PATCH 3/3] drm/i915: HSW FBC WaFbcDisableDpfcClockGating

2013-04-08 Thread Rodrigo Vivi
Display register 46500h bit 23 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915