On Sat, 2013-11-02 at 21:07 -0700, Ben Widawsky wrote:
> BDW caching works differently than the previous generations. Instead of
> having bits in the PTE which directly control how the page is cached,
> the 3 PTE bits PWT PCD and PAT provide an index into a PAT defined by
> register 0x40e0. This st
On Sat, Nov 02, 2013 at 09:07:19PM -0700, Ben Widawsky wrote:
> +static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
> +{
> +#define GEN8_PPAT_UC (0<<0)
> +#define GEN8_PPAT_WC (1<<0)
> +#define GEN8_PPAT_WT (2<<0)
> +#define GEN8_PPAT_WB (3<<0)
>
BDW caching works differently than the previous generations. Instead of
having bits in the PTE which directly control how the page is cached,
the 3 PTE bits PWT PCD and PAT provide an index into a PAT defined by
register 0x40e0. This style of caching is functionally equivalent to how
it works on HS
