Quoting Mika Kuoppala (2019-01-14 15:01:59)
> Chris Wilson writes:
> > unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
> > {
> > - unsigned long val;
> > + intel_wakeref_t wakeref;
> > + unsigned long val = 0;
> >
> > if (!IS_GEN(dev_priv, 5))
> >
Chris Wilson writes:
> Currently Ironlake operates under the assumption that rpm awake (and its
> error checking is disabled). As such, we have missed a few places where we
> access registers without taking the rpm wakeref and thus trigger
> warnings. intel_ips being one culprit.
>
> As this invo
On 1/10/2019 02:11, Chris Wilson wrote:
Currently Ironlake operates under the assumption that rpm awake (and its
error checking is disabled). As such, we have missed a few places where we
access registers without taking the rpm wakeref and thus trigger
warnings. intel_ips being one culprit.
As t
Currently Ironlake operates under the assumption that rpm awake (and its
error checking is disabled). As such, we have missed a few places where we
access registers without taking the rpm wakeref and thus trigger
warnings. intel_ips being one culprit.
As this involved adding a potentially sleeping
