On Wed, Mar 28, 2018 at 02:57:57PM -0700, Paulo Zanoni wrote:
> There's a lot of code for the PLL enabling, so let's first only
> introduce the register definitions in order to make patch reviewing a
> little easier.
>
> v2: Coding style (Jani).
> v3: Preparation for upstreaming.
> v4: Fix MG_CLKT
There's a lot of code for the PLL enabling, so let's first only
introduce the register definitions in order to make patch reviewing a
little easier.
v2: Coding style (Jani).
v3: Preparation for upstreaming.
v4: Fix MG_CLKTOP2_CORECLKCTL1 address and random typos (James).
Cc: James Ausmus
Signed-
