[Intel-gfx] [PATCH 2/6] drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue

2013-05-06 Thread Rodrigo Vivi
Display register 42000h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drive

[Intel-gfx] [PATCH 2/6] drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue

2013-04-25 Thread Rodrigo Vivi
Display register 42000h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Reviewed-by: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drive

Re: [Intel-gfx] [PATCH 2/6] drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue

2013-04-24 Thread Ville Syrjälä
On Tue, Apr 23, 2013 at 02:52:17PM -0300, Rodrigo Vivi wrote: > Display register 42000h bit 22 must be set to 1b for the entire time that > Frame Buffer Compression is enabled. > > Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_pm.c | 2 ++ > 1 file

[Intel-gfx] [PATCH 2/6] drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue

2013-04-23 Thread Rodrigo Vivi
Display register 42000h bit 22 must be set to 1b for the entire time that Frame Buffer Compression is enabled. Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c i