On Thu, Apr 09, 2015 at 04:26:19PM +0300, Imre Deak wrote:
> On Fri, 2015-04-03 at 18:13 -0700, jeff.mc...@intel.com wrote:
> > From: Jeff McGee
> >
> > Modify the Gen9 SSEU info initialization logic to support
> > Broxton. Broxton reuses the SKL fuse registers but has at most
> > 1 slice and 6 E
On Fri, 2015-04-03 at 18:13 -0700, jeff.mc...@intel.com wrote:
> From: Jeff McGee
>
> Modify the Gen9 SSEU info initialization logic to support
> Broxton. Broxton reuses the SKL fuse registers but has at most
> 1 slice and 6 EU per subslice.
>
> Signed-off-by: Jeff McGee
> ---
> drivers/gpu/dr
From: Jeff McGee
Modify the Gen9 SSEU info initialization logic to support
Broxton. Broxton reuses the SKL fuse registers but has at most
1 slice and 6 EU per subslice.
Signed-off-by: Jeff McGee
---
drivers/gpu/drm/i915/i915_dma.c | 47 ++---
drivers/gpu/drm
