Re: [Intel-gfx] [PATCH 2/3] drm/i915: Align DSPSURF to 128k on VLV/CHV

2015-06-11 Thread Arun R Murthy
On Thursday 11 June 2015 07:01 PM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä VLV/CHV have problems with 4k aligned linear scanout buffers. The VLV docs got updated at some point to say that we need to align them to 128k, just like we do on gen4. So far I've seen the problem man

Re: [Intel-gfx] [PATCH 2/3] drm/i915: Align DSPSURF to 128k on VLV/CHV

2015-06-11 Thread Clint Taylor
On 06/11/2015 06:31 AM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä VLV/CHV have problems with 4k aligned linear scanout buffers. The VLV docs got updated at some point to say that we need to align them to 128k, just like we do on gen4. So far I've seen the problem manifest when t

[Intel-gfx] [PATCH 2/3] drm/i915: Align DSPSURF to 128k on VLV/CHV

2015-06-11 Thread ville . syrjala
From: Ville Syrjälä VLV/CHV have problems with 4k aligned linear scanout buffers. The VLV docs got updated at some point to say that we need to align them to 128k, just like we do on gen4. So far I've seen the problem manifest when the stride is an odd multiple of 512 bytes, and the surface addr