Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Enable 2nd DBuf slice only when needed

2018-11-05 Thread Imre Deak
On Thu, Apr 26, 2018 at 07:55:16PM +0530, Mahesh Kumar wrote: > ICL has two slices of DBuf, each slice of size 1024 blocks. > We should not always enable slice-2. It should be enabled only if > display total required BW is > 12GBps OR more than 1 pipes are enabled. > > Changes since V1: > - typec

[Intel-gfx] [PATCH 2/3] drm/i915/icl: Enable 2nd DBuf slice only when needed

2018-04-26 Thread Mahesh Kumar
ICL has two slices of DBuf, each slice of size 1024 blocks. We should not always enable slice-2. It should be enabled only if display total required BW is > 12GBps OR more than 1 pipes are enabled. Changes since V1: - typecast total_data_rate to u64 before multiplication to solve any possible

Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Enable 2nd DBuf slice only when needed

2018-04-25 Thread Rodrigo Vivi
On Thu, Apr 05, 2018 at 02:47:55PM +0530, Mahesh Kumar wrote: > ICL has two slices of DBuf, each slice of size 1024 blocks. > We should not always enable slice-2. It should be enabled only if > display total required BW is > 12GBps OR more than 1 pipes are enabled. > > Changes since V1: > - typeca

Re: [Intel-gfx] [PATCH 2/3] drm/i915/icl: Enable 2nd DBuf slice only when needed

2018-04-25 Thread Rodrigo Vivi
On Thu, Apr 05, 2018 at 11:30:18AM +0530, Mahesh Kumar wrote: > ICL has two slices of DBuf, each slice of size 1024 blocks. > We should not always enable slice-2. It should be enabled only if > display total required BW is > 12GBps OR more than 1 pipes are enabled. > > Changes since V1: > - typec

[Intel-gfx] [PATCH 2/3] drm/i915/icl: Enable 2nd DBuf slice only when needed

2018-04-05 Thread Mahesh Kumar
ICL has two slices of DBuf, each slice of size 1024 blocks. We should not always enable slice-2. It should be enabled only if display total required BW is > 12GBps OR more than 1 pipes are enabled. Changes since V1: - typecast total_data_rate to u64 before multiplication to solve any possible

[Intel-gfx] [PATCH 2/3] drm/i915/icl: Enable 2nd DBuf slice only when needed

2018-04-04 Thread Mahesh Kumar
ICL has two slices of DBuf, each slice of size 1024 blocks. We should not always enable slice-2. It should be enabled only if display total required BW is > 12GBps OR more than 1 pipes are enabled. Changes since V1: - typecast total_data_rate to u64 before multiplication to solve any possible