Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Wait for CSB entries on Tigerlake

2020-08-15 Thread Chris Wilson
Quoting Chang, Bruce (2020-08-15 03:16:58) > On 8/14/2020 5:36 PM, Chang, Bruce wrote: > > > @@ -2498,9 +2498,22 @@ invalidate_csb_entries(const u64 *first, > const u64 *last) >     */ >    static inline bool gen12_csb_parse(const u64 *csb) >    { > - u64 entry =

Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Wait for CSB entries on Tigerlake

2020-08-15 Thread Chris Wilson
Quoting Chang, Bruce (2020-08-15 01:36:10) > > >>> @@ -2498,9 +2498,22 @@ invalidate_csb_entries(const u64 *first, const u64 > >>> *last) > >>> */ > >>>static inline bool gen12_csb_parse(const u64 *csb) > >>>{ > >>> - u64 entry = READ_ONCE(*csb); > >>> - bool ctx_away_valid =

Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Wait for CSB entries on Tigerlake

2020-08-14 Thread Chang, Bruce
On 8/14/2020 5:36 PM, Chang, Bruce wrote: @@ -2498,9 +2498,22 @@ invalidate_csb_entries(const u64 *first, const u64 *last)     */    static inline bool gen12_csb_parse(const u64 *csb)    { - u64 entry = READ_ONCE(*csb); - bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_32_bits(entry));

Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Wait for CSB entries on Tigerlake

2020-08-14 Thread Chang, Bruce
@@ -2498,9 +2498,22 @@ invalidate_csb_entries(const u64 *first, const u64 *last) */ static inline bool gen12_csb_parse(const u64 *csb) { - u64 entry = READ_ONCE(*csb); - bool ctx_away_valid = GEN12_CSB_CTX_VALID(upper_32_bits(entry)); - bool new_queue = + bool ctx_away

Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Wait for CSB entries on Tigerlake

2020-08-14 Thread Chris Wilson
Quoting Chang, Bruce (2020-08-14 19:07:53) > On 8/14/2020 8:57 AM, Chris Wilson wrote: > > On Tigerlake, we are seeing a repeat of commit d8f505311717 ("drm/i915/icl: > > Forcibly evict stale csb entries") where, presumably, due to a missing > > Global Observation Point synchronisation, the write p

Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Wait for CSB entries on Tigerlake

2020-08-14 Thread Chang, Bruce
On 8/14/2020 8:57 AM, Chris Wilson wrote: On Tigerlake, we are seeing a repeat of commit d8f505311717 ("drm/i915/icl: Forcibly evict stale csb entries") where, presumably, due to a missing Global Observation Point synchronisation, the write pointer of the CSB ringbuffer is updated _prior_ to the

[Intel-gfx] [PATCH 2/3] drm/i915/gt: Wait for CSB entries on Tigerlake

2020-08-14 Thread Chris Wilson
On Tigerlake, we are seeing a repeat of commit d8f505311717 ("drm/i915/icl: Forcibly evict stale csb entries") where, presumably, due to a missing Global Observation Point synchronisation, the write pointer of the CSB ringbuffer is updated _prior_ to the contents of the ringbuffer. That is we see t