On Sat, 15 May 2010 01:54:56 -0700
Andy Isaacson wrote:
> On Mon, May 10, 2010 at 10:00:46PM -0400, Andrew Morton wrote:
> > > + int i;
> > > + u16 avg;
> > > +
> > > + for (i = 0; i < IPS_SAMPLE_COUNT; i++)
> > > + total += (u64)(array[i] * 100);
> >
> > Actually, that does work. Someh
On Mon, May 10, 2010 at 10:00:46PM -0400, Andrew Morton wrote:
> > + int i;
> > + u16 avg;
> > +
> > + for (i = 0; i < IPS_SAMPLE_COUNT; i++)
> > + total += (u64)(array[i] * 100);
>
> Actually, that does work. Somehow the compiler will promote array[i]
> to u64 _before_ doing the
On Mon, 10 May 2010 22:00:46 -0400
Andrew Morton wrote:
> I applied both patches, did `make allmodconfig' and tried to make
> drivers/platform/x86/intel_ips.o:
>
> drivers/platform/x86/intel_ips.c: In function 'ips_get_i915_syms':
> drivers/platform/x86/intel_ips.c:1361: error: 'i915_read_mch_val
On Tue, 11 May 2010 11:38:36 -0400
Andrew Morton wrote:
> On Tue, 11 May 2010 11:18:54 -0700 Jesse Barnes
> wrote:
>
> > > > > +#define thm_writeb(off, val) writeb((val), ips->regmap + (off))
> > > > > +#define thm_writew(off, val) writew((val), ips->regmap + (off))
> > > > > +#define thm_writ
On Tue, 11 May 2010 11:18:54 -0700 Jesse Barnes
wrote:
> > > > +#define thm_writeb(off, val) writeb((val), ips->regmap + (off))
> > > > +#define thm_writew(off, val) writew((val), ips->regmap + (off))
> > > > +#define thm_writel(off, val) writel((val), ips->regmap + (off))
> > >
> > > ick.
> >
On Tue, 11 May 2010 07:59:19 -0700
Jesse Barnes wrote:
> On Mon, 10 May 2010 22:00:46 -0400
> Andrew Morton wrote:
> > > +#define thm_readb(off) readb(ips->regmap + (off))
> > > +#define thm_readw(off) readw(ips->regmap + (off))
> > > +#define thm_readl(off) readl(ips->regmap + (off))
> > > +#de
On Mon, 10 May 2010 22:00:46 -0400
Andrew Morton wrote:
> > +#define thm_readb(off) readb(ips->regmap + (off))
> > +#define thm_readw(off) readw(ips->regmap + (off))
> > +#define thm_readl(off) readl(ips->regmap + (off))
> > +#define thm_readq(off) readq(ips->regmap + (off))
> > +
> > +#define thm
On Mon, 10 May 2010 14:26:52 -0700 Jesse Barnes
wrote:
> Intel Core i3/5 platforms with integrated graphics support both CPU and
> GPU turbo mode. CPU turbo mode is opportunistic: the CPU will use any
> available power to increase core frequencies if thermal headroom is
> available. The GPU si
Intel Core i3/5 platforms with integrated graphics support both CPU and
GPU turbo mode. CPU turbo mode is opportunistic: the CPU will use any
available power to increase core frequencies if thermal headroom is
available. The GPU side is more manual however; the graphics driver
must monitor GPU po
On Tue, 13 Apr 2010 21:24:53 +0200
Pavel Machek wrote:
> Hi!
>
> > Intel Core i3/5 platforms with integrated graphics support both CPU and
> > GPU turbo mode. CPU turbo mode is opportunistic: the CPU will use any
> > available power to increase core frequencies if thermal headroom is
> > availa
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