Re: [Intel-gfx] [PATCH 2/2] drm/i915: fix D_COMP usage on BDW

2014-07-09 Thread Daniel Vetter
On Wed, Jul 09, 2014 at 05:35:52PM +0100, Damien Lespiau wrote: > On Fri, Jul 04, 2014 at 11:59:58AM -0300, Paulo Zanoni wrote: > > From: Paulo Zanoni > > > > On HSW, the D_COMP register can be accessed through the mailbox (read > > and write) or through MMIO on a MCHBAR offset (read only). On BD

Re: [Intel-gfx] [PATCH 2/2] drm/i915: fix D_COMP usage on BDW

2014-07-09 Thread Damien Lespiau
On Fri, Jul 04, 2014 at 11:59:58AM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > On HSW, the D_COMP register can be accessed through the mailbox (read > and write) or through MMIO on a MCHBAR offset (read only). On BDW, the > access should be done through MMIO on another address. So to acco

[Intel-gfx] [PATCH 2/2] drm/i915: fix D_COMP usage on BDW

2014-07-04 Thread Paulo Zanoni
From: Paulo Zanoni On HSW, the D_COMP register can be accessed through the mailbox (read and write) or through MMIO on a MCHBAR offset (read only). On BDW, the access should be done through MMIO on another address. So to account for all these cases, create hsw_read_dcomp() with the correct implem