t;>
> >> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander
> >> ; Hiremath, Shashidhar
> >>
> >> Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot
> >> for GLK DSI
> >>
> >> On Mon, 15 May 2017
r
>> ; Hiremath, Shashidhar
>>
>> Subject: RE: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK
>> DSI
>>
>> On Mon, 15 May 2017, "Chauhan, Madhav"
>> wrote:
>> >> -Original Message-
>> >> From:
t;>
> >> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander
> >> ; Hiremath, Shashidhar
> >>
> >> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot
> >> for GLK DSI
> >>
> >> On Tue, 09 May 201
r
>> ; Hiremath, Shashidhar
>>
>> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/glk: Enable cold boot for GLK
>> DSI
>>
>> On Tue, 09 May 2017, Ville Syrjälä wrote:
>> > On Tue, May 09, 2017 at 06:59:25PM +0530, Madhav Chauhan wrote:
>> >> As p
> -Original Message-
> From: Nikula, Jani
> Sent: Monday, May 15, 2017 9:19 PM
> To: Ville Syrjälä ; Chauhan, Madhav
>
> Cc: intel-gfx@lists.freedesktop.org; Conselvan De Oliveira, Ander
> ; Hiremath, Shashidhar
>
> Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i91
On Tue, 09 May 2017, Ville Syrjälä wrote:
> On Tue, May 09, 2017 at 06:59:25PM +0530, Madhav Chauhan wrote:
>> As per BSEPC, if device ready bit is '0' in enable IO sequence
>> then its a cold boot/reset scenario eg: S3/S4 resume. In these
>> conditions we need to program certain registers and pre
On Tue, May 09, 2017 at 06:59:25PM +0530, Madhav Chauhan wrote:
> As per BSEPC, if device ready bit is '0' in enable IO sequence
> then its a cold boot/reset scenario eg: S3/S4 resume. In these
> conditions we need to program certain registers and prepare port
> from the middle of DSI enable sequen
As per BSEPC, if device ready bit is '0' in enable IO sequence
then its a cold boot/reset scenario eg: S3/S4 resume. In these
conditions we need to program certain registers and prepare port
from the middle of DSI enable sequence otherwise feature like S3/S4
doesn't work.
Signed-off-by: Madhav Cha
As per BSEPC, if device ready bit is '0' in enable IO sequence
then its a cold boot/reset scenario eg: S3/S4 resume. In these
conditions we need to program certain registers and prepare port
from the middle of DSI enable sequence otherwise feature like S3/S4
doesn't work.
Signed-off-by: Madhav Cha
