On Mon, Jun 08, 2015 at 08:20:48PM +0100, Damien Lespiau wrote:
> On Fri, Jun 05, 2015 at 03:58:23PM -0700, Rodrigo Vivi wrote:
> > Due to RTL Bug, GAM does not support enabling GTT cache when
> > big pages are also turned on. This leads to GAM reporting
> > incorrect data and address.
>
> We don'
On Fri, Jun 05, 2015 at 03:58:23PM -0700, Rodrigo Vivi wrote:
> Due to RTL Bug, GAM does not support enabling GTT cache when
> big pages are also turned on. This leads to GAM reporting
> incorrect data and address.
We don't use big pages, so we can leave GTT caching enabled until we
support them (
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6548
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
Due to RTL Bug, GAM does not support enabling GTT cache when
big pages are also turned on. This leads to GAM reporting
incorrect data and address.
For A0 let the register GTT_CACHE_EN use the default value[0x].
For B0 onwards enable the GTT cache by setting the GTT_CACHE_EN[04024h]
to value
