Re: [Intel-gfx] [PATCH 15/15] drm/i915: Add CHV PHY LDO power sanity checks

2015-09-01 Thread Daniel Vetter
On Thu, Aug 27, 2015 at 10:09:37AM +0530, Deepak wrote: > > > On 07/09/2015 02:16 AM, ville.syrj...@linux.intel.com wrote: > >From: Ville Syrjälä > > > >At various points when changing the DPIO lane/phy power states, > >construct an expected value of the DISPLAY_PHY_STATUS register > >and compar

Re: [Intel-gfx] [PATCH 15/15] drm/i915: Add CHV PHY LDO power sanity checks

2015-08-26 Thread Deepak
On 07/09/2015 02:16 AM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä At various points when changing the DPIO lane/phy power states, construct an expected value of the DISPLAY_PHY_STATUS register and compare it with the real thing. To construct the expected value we look at our s

[Intel-gfx] [PATCH 15/15] drm/i915: Add CHV PHY LDO power sanity checks

2015-07-08 Thread ville . syrjala
From: Ville Syrjälä At various points when changing the DPIO lane/phy power states, construct an expected value of the DISPLAY_PHY_STATUS register and compare it with the real thing. To construct the expected value we look at our shadow PHY_CONTROL register value (which should match what we've j