Re: [Intel-gfx] [PATCH 10/10] drm/i915/psr: EDP_PSR_PERF_CNT not valid for psr2

2017-01-05 Thread Rodrigo Vivi
On Mon, Jan 02, 2017 at 05:01:03PM +0530, vathsala nagaraju wrote: > PSR1 and PSR2 enable sequence are mutually exclusive. > Register SRD_PERF_COUNT increments while system is in psr1. > This register is not valid for psr2.while in psr2,SRD_PERF_COUNT > is always 0. > Reporting psr perfcount from S

[Intel-gfx] [PATCH 10/10] drm/i915/psr: EDP_PSR_PERF_CNT not valid for psr2

2017-01-02 Thread vathsala nagaraju
PSR1 and PSR2 enable sequence are mutually exclusive. Register SRD_PERF_COUNT increments while system is in psr1. This register is not valid for psr2.while in psr2,SRD_PERF_COUNT is always 0. Reporting psr perfcount from SRD_PERF_COUNT is not valid for psr2 case. Also, if dc6 is disabled via kernel

[Intel-gfx] [PATCH 10/10] drm/i915/psr: EDP_PSR_PERF_CNT not valid for psr2

2016-12-29 Thread vathsala nagaraju
PSR1 and PSR2 enable sequence are mutually exclusive. Register SRD_PERF_COUNT increments while system is in psr1. This register is not valid for psr2.while in psr2,SRD_PERF_COUNT is always 0. Reporting psr perfcount from SRD_PERF_COUNT is not valid for psr2 case. Also, if dc6 is disabled via kernel