Re: [Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

2014-04-22 Thread Mateo Lozano, Oscar
> Subject: [Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size > with macro > > For readibility and guess at the meaning behind the constants. > > v2: Claim only the meagerest connections with reality. > > Signed-off-by: Chris Wilson

[Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

2014-04-09 Thread Chris Wilson
For readibility and guess at the meaning behind the constants. v2: Claim only the meagerest connections with reality. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_ringbuffer.c | 34 - 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/d

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

2014-04-03 Thread Daniel Vetter
On Thu, Apr 03, 2014 at 04:23:05PM +0100, Chris Wilson wrote: > On Thu, Apr 03, 2014 at 05:16:16PM +0200, Daniel Vetter wrote: > > btw the 1k thing at least on i865G is iirc just the writeout fifo between > > the cpu and the gmch to paper over FSB latencies (or whatever irked hw > > designers). >

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

2014-04-03 Thread Chris Wilson
On Thu, Apr 03, 2014 at 05:16:16PM +0200, Daniel Vetter wrote: > btw the 1k thing at least on i865G is iirc just the writeout fifo between > the cpu and the gmch to paper over FSB latencies (or whatever irked hw > designers). Isn't there a 1024 byte supercacheline for msaa as well? At least that s

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

2014-04-03 Thread Daniel Vetter
On Thu, Apr 03, 2014 at 07:45:40AM +0100, Chris Wilson wrote: > On Wed, Apr 02, 2014 at 02:57:11PM -0700, Jesse Barnes wrote: > > On Wed, 2 Apr 2014 16:36:06 +0100 > > Chris Wilson wrote: > > > > > For readibility and guess at the meaning behind the constants. > > > > > > Signed-off-by: Chris W

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

2014-04-02 Thread Chris Wilson
On Wed, Apr 02, 2014 at 02:57:11PM -0700, Jesse Barnes wrote: > On Wed, 2 Apr 2014 16:36:06 +0100 > Chris Wilson wrote: > > > For readibility and guess at the meaning behind the constants. > > > > Signed-off-by: Chris Wilson > > --- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 29 +++

Re: [Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

2014-04-02 Thread Jesse Barnes
On Wed, 2 Apr 2014 16:36:06 +0100 Chris Wilson wrote: > For readibility and guess at the meaning behind the constants. > > Signed-off-by: Chris Wilson > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 29 - > 1 file changed, 16 insertions(+), 13 deletions(-) > > d

[Intel-gfx] [PATCH 1/6] drm/i915: Replace hardcoded cacheline size with macro

2014-04-02 Thread Chris Wilson
For readibility and guess at the meaning behind the constants. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_ringbuffer.c | 29 - 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9