On Sat, Nov 22, 2014 at 11:05:15AM +, Chris Wilson wrote:
> On Fri, Nov 21, 2014 at 09:54:25PM +0200, ville.syrj...@linux.intel.com wrote:
> > + /* assert reset for at least 20 usec */
> > + pci_write_config_byte(dev->pdev, I965_GDRST, GRDOM_RESET_ENABLE);
>
> Is this an UC write or do we
On Fri, Nov 21, 2014 at 09:54:25PM +0200, ville.syrj...@linux.intel.com wrote:
> + /* assert reset for at least 20 usec */
> + pci_write_config_byte(dev->pdev, I965_GDRST, GRDOM_RESET_ENABLE);
Is this an UC write or do we need to post?
> + udelay(20);
> pci_write_config_byte(dev
From: Ville Syrjälä
On pre-ctg the reset bit directly controls the reset signal. We must
assert it for >=20usec and then deassert it. Bit 1 is a RO status bit
which should also go down when the reset is no longer asserted.
Tested-by: Kenneth Graunke
Signed-off-by: Ville Syrjälä
---
drivers/gp
