Re: [Intel-gfx] [PATCH 07/12] drm/i915/bdw: Support 64 bit PPGTT in lrc mode

On Fri, Feb 20, 2015 at 11:16 PM, Michel Thierry wrote: > In 64b (48bit canonical) PPGTT addressing, the PDP0 register contains > the base address to PML4, while the other PDP registers are ignored. > > Also, the addressing mode must be specified in every context descriptor. > > Signed-off-by: Mic

[Intel-gfx] [PATCH 07/12] drm/i915/bdw: Support 64 bit PPGTT in lrc mode

In 64b (48bit canonical) PPGTT addressing, the PDP0 register contains the base address to PML4, while the other PDP registers are ignored. Also, the addressing mode must be specified in every context descriptor. Signed-off-by: Michel Thierry --- drivers/gpu/drm/i915/intel_lrc.c | 167 ++