Re: [Intel-gfx] [PATCH 07/10] drm/i915: print Gen5+ CPU poison interrupts

2013-02-14 Thread Ben Widawsky
On Thu, 14 Feb 2013 18:35:32 -0200 Paulo Zanoni wrote: > Hi > > 2013/2/9 Ben Widawsky : > > On Fri, 8 Feb 2013 11:42:39 -0800 > > Jesse Barnes wrote: > > > >> On Fri, 8 Feb 2013 17:35:18 -0200 > >> Paulo Zanoni wrote: > >> > >> > From: Paulo Zanoni > >> > > >> > On ILK/SNB all we need to do

Re: [Intel-gfx] [PATCH 07/10] drm/i915: print Gen5+ CPU poison interrupts

2013-02-14 Thread Paulo Zanoni
Hi 2013/2/9 Ben Widawsky : > On Fri, 8 Feb 2013 11:42:39 -0800 > Jesse Barnes wrote: > >> On Fri, 8 Feb 2013 17:35:18 -0200 >> Paulo Zanoni wrote: >> >> > From: Paulo Zanoni >> > >> > On ILK/SNB all we need to do is to enable the "poison" bit, but on >> > IVB/HSW we need to enable the CPU erro

Re: [Intel-gfx] [PATCH 07/10] drm/i915: print Gen5+ CPU poison interrupts

2013-02-09 Thread Ben Widawsky
On Fri, 8 Feb 2013 11:42:39 -0800 Jesse Barnes wrote: > On Fri, 8 Feb 2013 17:35:18 -0200 > Paulo Zanoni wrote: > > > From: Paulo Zanoni > > > > On ILK/SNB all we need to do is to enable the "poison" bit, but on > > IVB/HSW we need to enable the CPU error interrupt register, which is > > res

Re: [Intel-gfx] [PATCH 07/10] drm/i915: print Gen5+ CPU poison interrupts

2013-02-08 Thread Jesse Barnes
On Fri, 8 Feb 2013 17:54:23 -0200 Paulo Zanoni wrote: > Hi > > 2013/2/8 Jesse Barnes : > > On Fri, 8 Feb 2013 17:35:18 -0200 > > Paulo Zanoni wrote: > > > >> From: Paulo Zanoni > >> > >> On ILK/SNB all we need to do is to enable the "poison" bit, but on > >> IVB/HSW we need to enable the CPU

Re: [Intel-gfx] [PATCH 07/10] drm/i915: print Gen5+ CPU poison interrupts

2013-02-08 Thread Paulo Zanoni
Hi 2013/2/8 Jesse Barnes : > On Fri, 8 Feb 2013 17:35:18 -0200 > Paulo Zanoni wrote: > >> From: Paulo Zanoni >> >> On ILK/SNB all we need to do is to enable the "poison" bit, but on >> IVB/HSW we need to enable the CPU error interrupt register, which is >> responsible not only for poison interr

Re: [Intel-gfx] [PATCH 07/10] drm/i915: print Gen5+ CPU poison interrupts

2013-02-08 Thread Jesse Barnes
On Fri, 8 Feb 2013 17:35:18 -0200 Paulo Zanoni wrote: > From: Paulo Zanoni > > On ILK/SNB all we need to do is to enable the "poison" bit, but on > IVB/HSW we need to enable the CPU error interrupt register, which is > responsible not only for poison interrupts, but also other things. > This i

[Intel-gfx] [PATCH 07/10] drm/i915: print Gen5+ CPU poison interrupts

2013-02-08 Thread Paulo Zanoni
From: Paulo Zanoni On ILK/SNB all we need to do is to enable the "poison" bit, but on IVB/HSW we need to enable the CPU error interrupt register, which is responsible not only for poison interrupts, but also other things. This includes the "unclaimed register" interrupt, so on the IVB irq handler