Re: [Intel-gfx] [PATCH 06/15] drm/i915: Move VLV/CHV prepare_pll later

On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä With DPIO powergating active on CHV, we can't even access the DPIO PLL registers until the lane power state overrides have been enabled. That will happen from the encoder .pre_pll_enable() hook, so move chv_prepa

Re: [Intel-gfx] [PATCH 06/15] drm/i915: Move VLV/CHV prepare_pll later

On 07/09/2015 02:15 AM, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä With DPIO powergating active on CHV, we can't even access the DPIO PLL registers until the lane power state overrides have been enabled. That will happen from the encoder .pre_pll_enable() hook, so move chv_prepa

[Intel-gfx] [PATCH 06/15] drm/i915: Move VLV/CHV prepare_pll later

From: Ville Syrjälä With DPIO powergating active on CHV, we can't even access the DPIO PLL registers until the lane power state overrides have been enabled. That will happen from the encoder .pre_pll_enable() hook, so move chv_prepare_pll() to happen after that point, which puts it just before ch