Re: [Intel-gfx] [PATCH 05/26] drm/i915: panel power sequencing for VLV eDP

2013-03-08 Thread Jesse Barnes
On Fri, 08 Mar 2013 15:51:44 +0200 Jani Nikula wrote: > > + } else { > > + pp_control_reg = PP_CONTROL; > > + pp_on_reg = PP_ON_DELAYS; > > + pp_off_reg = PP_OFF_DELAYS; > > + pp_div_reg = PP_DIVISOR; > > + } > > Is this else branch needed? ironlake_

Re: [Intel-gfx] [PATCH 05/26] drm/i915: panel power sequencing for VLV eDP

2013-03-08 Thread Jani Nikula
On Sat, 02 Mar 2013, Jesse Barnes wrote: > PPS register offsets have changed in Valleyview. > > Signed-off-by: Jesse Barnes > Signed-off-by: Gajanan Bhat > Signed-off-by: Vijay Purushothaman > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_reg.h |9 ++ > drivers/gpu/dr

[Intel-gfx] [PATCH 05/26] drm/i915: panel power sequencing for VLV eDP

2013-03-01 Thread Jesse Barnes
PPS register offsets have changed in Valleyview. Signed-off-by: Jesse Barnes Signed-off-by: Gajanan Bhat Signed-off-by: Vijay Purushothaman Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_reg.h |9 ++ drivers/gpu/drm/i915/intel_display.c |1 - drivers/gpu/drm/i915/intel