Re: [Intel-gfx] [PATCH 05/11] drm/i915: panel power sequencing for VLV eDP v2

2013-04-02 Thread Daniel Vetter
On Thu, Mar 28, 2013 at 09:55:41AM -0700, Jesse Barnes wrote: > PPS register offsets have changed in Valleyview. > > v2: don't clobber port select bits on VLV when fixing up PPS timings > don't bother with G4x PPS regs (Jani) > > Signed-off-by: Jesse Barnes > Signed-off-by: Gajanan Bhat > S

[Intel-gfx] [PATCH 05/11] drm/i915: panel power sequencing for VLV eDP v2

2013-03-28 Thread Jesse Barnes
PPS register offsets have changed in Valleyview. v2: don't clobber port select bits on VLV when fixing up PPS timings don't bother with G4x PPS regs (Jani) Signed-off-by: Jesse Barnes Signed-off-by: Gajanan Bhat Signed-off-by: Vijay Purushothaman Signed-off-by: Ben Widawsky --- drivers/g