Re: [Intel-gfx] [PATCH 04/26] drm/i915: update VLV PLL and DPIO code

2013-03-08 Thread Jesse Barnes
On Fri, 08 Mar 2013 15:33:32 +0200 Jani Nikula wrote: > > + intel_dpio_write(dev_priv, 0x8438, 0x00760018); > > + intel_dpio_write(dev_priv, 0x845c, 0x00400888); > > + > > + intel_dpio_write(dev_priv, 0x8400, 0x10080); > > + intel_dpio_write(dev_priv, 0x840

Re: [Intel-gfx] [PATCH 04/26] drm/i915: update VLV PLL and DPIO code

2013-03-08 Thread Jani Nikula
On Sat, 02 Mar 2013, Jesse Barnes wrote: > From: Pallavi G > > In Valleyview voltage swing, pre-emphasis and lane control registers can > be programmed only through the h/w side band fabric. Update > vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the > appropriate programming. > > W

Re: [Intel-gfx] [PATCH 04/26] drm/i915: update VLV PLL and DPIO code

2013-03-05 Thread Jani Nikula
On Sat, 02 Mar 2013, Jesse Barnes wrote: > From: Pallavi G > > In Valleyview voltage swing, pre-emphasis and lane control registers can > be programmed only through the h/w side band fabric. Update > vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the > appropriate programming. > > W

Re: [Intel-gfx] [PATCH 04/26] drm/i915: update VLV PLL and DPIO code

2013-03-03 Thread Daniel Vetter
On Fri, Mar 01, 2013 at 02:08:20PM -0800, Jesse Barnes wrote: > From: Pallavi G > > In Valleyview voltage swing, pre-emphasis and lane control registers can > be programmed only through the h/w side band fabric. Update > vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the > appropria

Re: [Intel-gfx] [PATCH 04/26] drm/i915: update VLV PLL and DPIO code

2013-03-01 Thread Jesse Barnes
On Fri, 1 Mar 2013 14:08:20 -0800 Jesse Barnes wrote: > From: Pallavi G > > In Valleyview voltage swing, pre-emphasis and lane control registers can > be programmed only through the h/w side band fabric. Update > vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the > appropriate pr

Re: [Intel-gfx] [PATCH 04/26] drm/i915: update VLV PLL and DPIO code

2013-03-01 Thread Jesse Barnes
On Fri, 1 Mar 2013 14:08:20 -0800 Jesse Barnes wrote: > From: Pallavi G > > In Valleyview voltage swing, pre-emphasis and lane control registers can > be programmed only through the h/w side band fabric. Update > vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the > appropriate pr

[Intel-gfx] [PATCH 04/26] drm/i915: update VLV PLL and DPIO code

2013-03-01 Thread Jesse Barnes
From: Pallavi G In Valleyview voltage swing, pre-emphasis and lane control registers can be programmed only through the h/w side band fabric. Update vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the appropriate programming. We need to make sure that the tx lane reset occurs in bot