On Tue, 03 Dec 2019, Anshuamn Gupta wrote:
> On 2019-11-28 at 16:05:03 +0200, Jani Nikula wrote:
>> On Mon, 18 Nov 2019, Anshuman Gupta wrote:
>> > Putting down the AUX power domain reference count in
>> > edp vdd off async sequence takes too much of time
>> > (relative to panel power cycle delay
On 2019-11-28 at 16:05:03 +0200, Jani Nikula wrote:
> On Mon, 18 Nov 2019, Anshuman Gupta wrote:
> > Putting down the AUX power domain reference count in
> > edp vdd off async sequence takes too much of time
> > (relative to panel power cycle delay) therefore it make sense
> > to expose the panel
On Mon, 18 Nov 2019, Anshuman Gupta wrote:
> Putting down the AUX power domain reference count in
> edp vdd off async sequence takes too much of time
> (relative to panel power cycle delay) therefore it make sense
> to expose the panel power cycle delay to i915_panel_timings
> along with other del
Putting down the AUX power domain reference count in
edp vdd off async sequence takes too much of time
(relative to panel power cycle delay) therefore it make sense
to expose the panel power cycle delay to i915_panel_timings
along with other delays.
It can be use by DC state IGT to wait for strict
