On Thu, Apr 18, 2013 at 11:51 PM, Jesse Barnes wrote:
> +static void valleyview_crtc_enable(struct drm_crtc *crtc)
> +{
> + struct drm_device *dev = crtc->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +
On Fri, Apr 19, 2013 at 1:05 AM, Jesse Barnes wrote:
> \o/ I'll call off the hit man and cancel my plane ticket. Thanks.
And I already looked eagerly forward to an epic showdown somewhere in
the Swiss Alps ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - h
On Thu, Apr 18, 2013 at 02:51:36PM -0700, Jesse Barnes wrote:
> In Valleyview voltage swing, pre-emphasis and lane control registers can
> be programmed only through the h/w side band fabric. Update
> vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the
> appropriate programming.
>
> W
In Valleyview voltage swing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric. Update
vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the
appropriate programming.
We need to make sure that the tx lane reset occurs in both the full mode
se
