Re: [Intel-gfx] [PATCH] drm/i915: tweak the ordering in cpu_write_needs_clflush

2022-06-27 Thread Gwan-gyeong Mun
Thanks for fixing this issue. Looks good to me. Reviewed-by: Gwan-gyeong Mun On 6/22/22 6:59 PM, Matthew Auld wrote: For imported dma-buf objects we leave the object as cache_coherent = 0 across all platforms, which is reasonable given that have no clue what the memory underneath is, and its n

[Intel-gfx] [PATCH] drm/i915: tweak the ordering in cpu_write_needs_clflush

2022-06-22 Thread Matthew Auld
For imported dma-buf objects we leave the object as cache_coherent = 0 across all platforms, which is reasonable given that have no clue what the memory underneath is, and its not like the driver can ever manually clflush the pages anyway (like with i915_gem_clflush_object) for such objects. Howeve