Re: [Intel-gfx] [PATCH] drm/i915: initialize gen6 rps work queue for Ironlake+

2011-05-18 Thread Jesse Barnes
On Wed, 18 May 2011 13:42:54 -0700 Keith Packard wrote: > On Wed, 18 May 2011 10:22:27 -0700, Jesse Barnes > wrote: > > > The work queue is only used on gen6, but gen6 and ilk share an irq > > handler. I could make the work queue init conditional on gen6 though, > > if that's what you're thin

Re: [Intel-gfx] [PATCH] drm/i915: initialize gen6 rps work queue for Ironlake+

2011-05-18 Thread Keith Packard
On Wed, 18 May 2011 10:22:27 -0700, Jesse Barnes wrote: > The work queue is only used on gen6, but gen6 and ilk share an irq > handler. I could make the work queue init conditional on gen6 though, > if that's what you're thinking. Probably a good idea, mostly as documentation for which chips i

Re: [Intel-gfx] [PATCH] drm/i915: initialize gen6 rps work queue for Ironlake+

2011-05-18 Thread Jesse Barnes
On Wed, 18 May 2011 18:37:48 +0200 Ian Romanick wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA1 > > On 05/18/2011 06:21 PM, Jesse Barnes wrote: > > Looks like I didn't merge Ben's RPS work queue stuff correctly with the > > new IRQ split code (diff was sparse enough that git didn't comp

Re: [Intel-gfx] [PATCH] drm/i915: initialize gen6 rps work queue for Ironlake+

2011-05-18 Thread Ian Romanick
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 05/18/2011 06:21 PM, Jesse Barnes wrote: > Looks like I didn't merge Ben's RPS work queue stuff correctly with the > new IRQ split code (diff was sparse enough that git didn't complain). > This should prevent null derefs on ILK+ due to the missing w

[Intel-gfx] [PATCH] drm/i915: initialize gen6 rps work queue for Ironlake+

2011-05-18 Thread Jesse Barnes
Looks like I didn't merge Ben's RPS work queue stuff correctly with the new IRQ split code (diff was sparse enough that git didn't complain). This should prevent null derefs on ILK+ due to the missing work queue. Signed-off-by: Jesse Barnes diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers