On Wed, Feb 8, 2017 at 6:33 PM, Ville Syrjälä
wrote:
> On Wed, Feb 08, 2017 at 06:10:31PM +, Robert Bragg wrote:
>> This workaround for BDW was incomplete as it also requires EUTC clock
>> gating to be disabled via UCGCTL1.
>
> IIRC that matches what I told Ben years ago when the w/a was first
On Wed, Feb 08, 2017 at 06:10:31PM +, Robert Bragg wrote:
> This workaround for BDW was incomplete as it also requires EUTC clock
> gating to be disabled via UCGCTL1.
IIRC that matches what I told Ben years ago when the w/a was first
being added, and matches what I put in the CHV code when it
This workaround for BDW was incomplete as it also requires EUTC clock
gating to be disabled via UCGCTL1.
Signed-off-by: Robert Bragg
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
b/drivers/gpu/drm/i915/int
