Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

On 28/03/2022 18:16, fei.y...@intel.com wrote: From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalid

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

>> +u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs) >> -static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs) > > I think all helpers which emit to ring take cs as the first argument so it > would be good to make this consistent. Updated the patch, please review

[Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

On 28/03/2022 04:16, fei.y...@intel.com wrote: From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalid

[Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

On 18/03/2022 18:08, fei.y...@intel.com wrote: From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalid

[Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

>> static u32 *gen12_emit_aux_table_inv(const i915_reg_t inv_reg, u32 *cs) >> { >> *cs++ = MI_LOAD_REGISTER_IMM(1); >> @@ -296,7 +272,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 >> mode) >> if (!HAS_FLAT_CCS(rq->engine->i915)) { >> aux_inv

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

On 18/03/2022 05:26, fei.y...@intel.com wrote: From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalid

[Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the

[Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

>> diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c >> b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c >> index 1c82caf525c3..0ec4986e4805 100644 >> --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c >> +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c >> @@ -37,6 +37,9 @@ int gen2_emit_flush(struct i915

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

On 04/03/2022 22:14, fei.y...@intel.com wrote: From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalid

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

>>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c >>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c >>> index e1470bb60f34..7e8552414275 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c >>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

>> @@ -157,6 +163,9 @@ int gen11_emit_flush_rcs(struct i915_request *rq, >> u32 mode) >> intel_ring_advance(rq, cs); >> } >> >> +/* hsdes: 1809175790. No fixup needed for gen11 rcs */ >> +rq->aux_inv_fixup = NULL; > > This is a little ugly to me. Can we just set this to

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

On Fri, 2022-03-04 at 14:14 -0800, fei.y...@intel.com wrote: > From: Fei Yang > > GPU hangs have been observed when multiple engines write to the > same aux_inv register at the same time. To avoid this each engine > should only invalidate its own auxiliary table. The function > gen12_emit_flush_x

[Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the

[Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the

Re: [Intel-gfx] [intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv (rev3)

Hi Chris, for some reason I didn't receive the review email, so I copied your comments from patchwork and faked this email. >> static void execlists_dequeue(struct intel_engine_cs *engine) >> { >> struct intel_engine_execlists * const execlists = &engine->execlists; >> @@ -1538,6 +1566,

Re: [Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

Quoting fei.y...@intel.com (2022-03-02 18:26:57) > From: Fei Yang > > GPU hangs have been observed when multiple engines write to the > same aux_inv register at the same time. To avoid this each engine > should only invalidate its own auxiliary table. The function > gen12_emit_flush_xcs() current

[Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the

[Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the

[Intel-gfx] [PATCH] drm/i915: avoid concurrent writes to aux_inv

From: Fei Yang GPU hangs have been observed when multiple engines write to the same aux_inv register at the same time. To avoid this each engine should only invalidate its own auxiliary table. The function gen12_emit_flush_xcs() currently invalidate the auxiliary table for all engines because the