On Fri, 06 Sep 2013, Daniel Vetter wrote:
> On Fri, Sep 06, 2013 at 07:40:05AM +0300, Jani Nikula wrote:
>> VLV has per-pipe PP registers. Set up power sequencing on mode set. The
>> connector init time setup is problematic, since we don't have a pipe at
>> that time. Cook up something.
>>
>> v2:
On Fri, Sep 06, 2013 at 07:40:05AM +0300, Jani Nikula wrote:
> VLV has per-pipe PP registers. Set up power sequencing on mode set. The
> connector init time setup is problematic, since we don't have a pipe at
> that time. Cook up something.
>
> v2:
> - use vlv_power_sequencer_pipe() also in _pp_{
VLV has per-pipe PP registers. Set up power sequencing on mode set. The
connector init time setup is problematic, since we don't have a pipe at
that time. Cook up something.
v2:
- use vlv_power_sequencer_pipe() also in _pp_{ctrl,stat}_reg()
- use PANEL_PORT_SELECT_DPC_VLV (Ville)
v3: make check
