On 06/07/15 16:41, Chris Wilson wrote:
On Mon, Jul 06, 2015 at 04:33:05PM +0200, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 02:16:54PM +0100, Dave Gordon wrote:
On 06/07/15 13:38, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 12:52:51PM +0100, Dave Gordon wrote:
On 03/07/15 16:42, Chris Wils
On Mon, Jul 06, 2015 at 04:33:05PM +0200, Daniel Vetter wrote:
> On Mon, Jul 06, 2015 at 02:16:54PM +0100, Dave Gordon wrote:
> > On 06/07/15 13:38, Daniel Vetter wrote:
> > >On Mon, Jul 06, 2015 at 12:52:51PM +0100, Dave Gordon wrote:
> > >>On 03/07/15 16:42, Chris Wilson wrote:
> > >>>On Fri, Jul
On 06/07/15 15:33, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 02:16:54PM +0100, Dave Gordon wrote:
On 06/07/15 13:38, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 12:52:51PM +0100, Dave Gordon wrote:
On 03/07/15 16:42, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluv
On Mon, Jul 06, 2015 at 02:16:54PM +0100, Dave Gordon wrote:
> On 06/07/15 13:38, Daniel Vetter wrote:
> >On Mon, Jul 06, 2015 at 12:52:51PM +0100, Dave Gordon wrote:
> >>On 03/07/15 16:42, Chris Wilson wrote:
> >>>On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
> In this WA we n
On 06/07/15 13:38, Daniel Vetter wrote:
On Mon, Jul 06, 2015 at 12:52:51PM +0100, Dave Gordon wrote:
On 03/07/15 16:42, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after PIPE_CONTROL
instruction
On Mon, Jul 06, 2015 at 12:52:51PM +0100, Dave Gordon wrote:
> On 03/07/15 16:42, Chris Wilson wrote:
> >On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
> >>In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
> >>PIPE_CONTROL
> >>instruction but there is a slight comp
On 06/07/2015 12:52, Dave Gordon wrote:
On 03/07/15 16:42, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after PIPE_CONTROL
instruction but there is a slight complication as this is applied in WA b
On 03/07/15 16:42, Chris Wilson wrote:
On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after PIPE_CONTROL
instruction but there is a slight complication as this is applied in WA batch
where the values are only initialize
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6719
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Fri, Jul 03, 2015 at 02:27:31PM +0100, Arun Siluvery wrote:
> In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
> PIPE_CONTROL
> instruction but there is a slight complication as this is applied in WA batch
> where the values are only initialized once.
> Dave identified an issu
In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after PIPE_CONTROL
instruction but there is a slight complication as this is applied in WA batch
where the values are only initialized once.
Dave identified an issue with the current implementation where the register
value
is read once a
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