On Thu, May 21, 2015 at 5:30 PM, Daniel Vetter wrote:
> On Thu, May 21, 2015 at 04:22:55PM +0100, Chris Wilson wrote:
>> On Thu, May 21, 2015 at 04:21:46PM +0200, Daniel Vetter wrote:
>> > Hm right. What about emphasising this a bit more in the comment:
>> >
>> > /*
>> > * Empirical evide
On 05/21/2015 06:00 AM, Chris Wilson wrote:
> On Tue, May 19, 2015 at 03:41:48PM +0100, Chris Wilson wrote:
>> On Mon, May 11, 2015 at 04:25:52PM +0100, Chris Wilson wrote:
>>> On Mon, May 11, 2015 at 12:34:37PM +0200, Daniel Vetter wrote:
On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson
On Thu, May 21, 2015 at 04:22:55PM +0100, Chris Wilson wrote:
> On Thu, May 21, 2015 at 04:21:46PM +0200, Daniel Vetter wrote:
> > Hm right. What about emphasising this a bit more in the comment:
> >
> > /*
> > * Empirical evidence indicates that we need a write barrier to
> > * make
On Thu, May 21, 2015 at 04:21:46PM +0200, Daniel Vetter wrote:
> Hm right. What about emphasising this a bit more in the comment:
>
> /*
>* Empirical evidence indicates that we need a write barrier to
>* make sure write-combined writes (both to the gtt, but also to
>*
On Thu, May 21, 2015 at 02:13:01PM +0100, Chris Wilson wrote:
> On Thu, May 21, 2015 at 03:07:54PM +0200, Daniel Vetter wrote:
> > On Thu, May 21, 2015 at 02:00:34PM +0100, Chris Wilson wrote:
> > > On Tue, May 19, 2015 at 03:41:48PM +0100, Chris Wilson wrote:
> > > > On Mon, May 11, 2015 at 04:25:
On Thu, May 21, 2015 at 03:07:54PM +0200, Daniel Vetter wrote:
> On Thu, May 21, 2015 at 02:00:34PM +0100, Chris Wilson wrote:
> > On Tue, May 19, 2015 at 03:41:48PM +0100, Chris Wilson wrote:
> > > On Mon, May 11, 2015 at 04:25:52PM +0100, Chris Wilson wrote:
> > > > On Mon, May 11, 2015 at 12:34:
On Thu, May 21, 2015 at 02:00:34PM +0100, Chris Wilson wrote:
> On Tue, May 19, 2015 at 03:41:48PM +0100, Chris Wilson wrote:
> > On Mon, May 11, 2015 at 04:25:52PM +0100, Chris Wilson wrote:
> > > On Mon, May 11, 2015 at 12:34:37PM +0200, Daniel Vetter wrote:
> > > > On Mon, May 11, 2015 at 08:51:
On Tue, May 19, 2015 at 03:41:48PM +0100, Chris Wilson wrote:
> On Mon, May 11, 2015 at 04:25:52PM +0100, Chris Wilson wrote:
> > On Mon, May 11, 2015 at 12:34:37PM +0200, Daniel Vetter wrote:
> > > On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson wrote:
> > > > With the advent of mmap(wc), w
On Mon, May 11, 2015 at 04:25:52PM +0100, Chris Wilson wrote:
> On Mon, May 11, 2015 at 12:34:37PM +0200, Daniel Vetter wrote:
> > On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson wrote:
> > > With the advent of mmap(wc), we have a path to write directly into
> > > active GPU buffers. When co
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6378
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV
On Mon, May 11, 2015 at 04:25:52PM +0100, Chris Wilson wrote:
> On Mon, May 11, 2015 at 12:34:37PM +0200, Daniel Vetter wrote:
> > On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson wrote:
> > > With the advent of mmap(wc), we have a path to write directly into
> > > active GPU buffers. When co
On Mon, May 11, 2015 at 12:34:37PM +0200, Daniel Vetter wrote:
> On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson wrote:
> > With the advent of mmap(wc), we have a path to write directly into
> > active GPU buffers. When combined with async updates (i.e. avoiding the
> > explicit domain manag
On Mon, May 11, 2015 at 12:34:37PM +0200, Daniel Vetter wrote:
> On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson wrote:
> > With the advent of mmap(wc), we have a path to write directly into
> > active GPU buffers. When combined with async updates (i.e. avoiding the
> > explicit domain manag
On Mon, May 11, 2015 at 08:51:36AM +0100, Chris Wilson wrote:
> With the advent of mmap(wc), we have a path to write directly into
> active GPU buffers. When combined with async updates (i.e. avoiding the
> explicit domain management along with the memory barriers and GPU
> stalls) we start to see
With the advent of mmap(wc), we have a path to write directly into
active GPU buffers. When combined with async updates (i.e. avoiding the
explicit domain management along with the memory barriers and GPU
stalls) we start to see the GPU read the wrong values from memory - i.e.
we have insufficient
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