Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 7140
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Tue, Aug 11, 2015 at 02:58:59PM +0200, Daniel Vetter wrote:
> On Tue, Aug 11, 2015 at 11:24:58AM +0100, Chris Wilson wrote:
> > On Tue, Aug 11, 2015 at 12:12:08PM +0200, Daniel Vetter wrote:
> > > On Mon, Aug 10, 2015 at 09:16:46PM +0100, Chris Wilson wrote:
> > > > If the set of pages is being
On Tue, Aug 11, 2015 at 11:24:58AM +0100, Chris Wilson wrote:
> On Tue, Aug 11, 2015 at 12:12:08PM +0200, Daniel Vetter wrote:
> > On Mon, Aug 10, 2015 at 09:16:46PM +0100, Chris Wilson wrote:
> > > If the set of pages is being imported from another device, we cannot
> > > assume that it is fully c
On Tue, Aug 11, 2015 at 12:12:08PM +0200, Daniel Vetter wrote:
> On Mon, Aug 10, 2015 at 09:16:46PM +0100, Chris Wilson wrote:
> > If the set of pages is being imported from another device, we cannot
> > assume that it is fully coherent with the CPU cache, so mark it as such.
> > However, if the so
On Mon, Aug 10, 2015 at 09:16:46PM +0100, Chris Wilson wrote:
> If the set of pages is being imported from another device, we cannot
> assume that it is fully coherent with the CPU cache, so mark it as such.
> However, if the source is the shared memory vgem allocator, we could
> treat the buffer a
If the set of pages is being imported from another device, we cannot
assume that it is fully coherent with the CPU cache, so mark it as such.
However, if the source is the shared memory vgem allocator, we could
treat the buffer as being cached (so long as all parties agree in the
case the same buff
