> -Original Message-
> From: Intel-gfx On Behalf Of Ville
> Syrjala
> Sent: Friday, March 11, 2022 11:29 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: sta...@vger.kernel.org
> Subject: [Intel-gfx] [PATCH] drm/i915: Reject unsupported TMDS rates on ICL+
>
> Fr
From: Ville Syrjälä
ICL+ PLLs can't genenerate certain frequencies. Running the PLL
algorithms through for all frequencies 25-594MHz we see a gap just
above 500 MHz. Specifically 500-522.8MHZ for TC PLLs, and 500-533.2
MHz for combo PHY PLLs. Reject those frequencies hdmi_port_clock_valid()
so th
