[Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-20 Thread Chris Wilson
VT-d may cause overfetch of the scanout PTE, both before and after the vma (depending on the scanout orientation). bspec recommends that we provide a tile-row in either directions, and suggests using 168 PTE, warning that the accesses will wrap around the ends of the GGTT. Currently, we fill the en

[Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-20 Thread Chris Wilson
VT-d may cause overfetch of the scanout PTE, both before and after the vma (depending on the scanout orientation). bspec recommends that we provide a tile-row in either directions, and suggests using 168 PTE, warning that the accesses will wrap around the ends of the GGTT. Currently, we fill the en

Re: [Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-11 Thread Chris Wilson
Quoting Matthew Auld (2021-02-11 17:00:20) > Throwing some color_adjust at it might be another option to consider. > Maybe something like: > > +static void i915_ggtt_color_adjust_vdt(const struct drm_mm_node *node, > + unsigned long color, > +

Re: [Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-11 Thread Matthew Auld
On 11/02/2021 15:19, Chris Wilson wrote: Quoting Matthew Auld (2021-02-11 14:25:41) On 10/02/2021 23:39, Chris Wilson wrote: VT-d may cause overfetch of the scanout PTE, both before and after the vma (depending on the scanout orientation). bspec recommends that we provide a tile-row in either d

Re: [Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-11 Thread Chris Wilson
Quoting Ville Syrjälä (2021-02-11 16:05:59) > On Wed, Feb 10, 2021 at 11:39:46PM +, Chris Wilson wrote: > > @@ -637,6 +642,13 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 > > alignment, u64 flags) > > alignment, vma->fence_alignment); > > } > >

Re: [Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-11 Thread Ville Syrjälä
On Wed, Feb 10, 2021 at 11:39:46PM +, Chris Wilson wrote: > VT-d may cause overfetch of the scanout PTE, both before and after the > vma (depending on the scanout orientation). bspec recommends that we > provide a tile-row in either directions, and suggests using 160 PTE, > warning that the acc

Re: [Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-11 Thread Chris Wilson
Quoting Matthew Auld (2021-02-11 14:25:41) > On 10/02/2021 23:39, Chris Wilson wrote: > > VT-d may cause overfetch of the scanout PTE, both before and after the > > vma (depending on the scanout orientation). bspec recommends that we > > provide a tile-row in either directions, and suggests using 1

Re: [Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-11 Thread Matthew Auld
On 10/02/2021 23:39, Chris Wilson wrote: VT-d may cause overfetch of the scanout PTE, both before and after the vma (depending on the scanout orientation). bspec recommends that we provide a tile-row in either directions, and suggests using 160 PTE, warning that the accesses will wrap around the

[Intel-gfx] [PATCH] drm/i915: Refine VT-d scanout workaround

2021-02-10 Thread Chris Wilson
VT-d may cause overfetch of the scanout PTE, both before and after the vma (depending on the scanout orientation). bspec recommends that we provide a tile-row in either directions, and suggests using 160 PTE, warning that the accesses will wrap around the ends of the GGTT. Currently, we fill the en