Re: [Intel-gfx] [PATCH] drm/i915: Only apply the SNB pipe control w/a to gen6

2012-08-08 Thread Daniel Vetter
On Fri, Jul 20, 2012 at 06:02:28PM +0100, Chris Wilson wrote: > The requirements for the sync flush to be emitted prior to the render > cache flush is only true for SandyBridge. On IvyBridge and friends we > can just emit the flushes with an inline CS stall. > > Signed-off-by: Chris Wilson Since

Re: [Intel-gfx] [PATCH] drm/i915: Only apply the SNB pipe control w/a to gen6

2012-07-20 Thread Ben Widawsky
On Fri, 20 Jul 2012 18:02:28 +0100 Chris Wilson wrote: > The requirements for the sync flush to be emitted prior to the render > cache flush is only true for SandyBridge. On IvyBridge and friends we > can just emit the flushes with an inline CS stall. > > Signed-off-by: Chris Wilson Tested-by:

[Intel-gfx] [PATCH] drm/i915: Only apply the SNB pipe control w/a to gen6

2012-07-20 Thread Chris Wilson
The requirements for the sync flush to be emitted prior to the render cache flush is only true for SandyBridge. On IvyBridge and friends we can just emit the flushes with an inline CS stall. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_ringbuffer.c | 33 +++---