Re: [Intel-gfx] [PATCH] drm/i915: Mark the GTT as uncached, not WC, for Cherryview

Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) Task id: 7209 -Summary- Platform Delta drm-intel-nightly Series Applied ILK

[Intel-gfx] [PATCH] drm/i915: Mark the GTT as uncached, not WC, for Cherryview

I traced a stability issue on my Braswell nuc to a lack of visibility of PTE writes into the GTT by the GPU. (The smoking gun was GPU hangs with random fault addresses but correct command streams). Adding clflushes or kicking the chipset flush harder had no effect, only disabling the WC cache for t