On Tue, Dec 10, 2013 at 12:36:34PM +0200, Jani Nikula wrote:
> On Tue, 10 Dec 2013, Vandana Kannan wrote:
> > If one mode of a internal panel has more than one refresh rate, then a
> > reduced
> > clock is found for the LFP (LVDS/eDP). This enables switching between low
> > and high frequency dyn
On Tue, 10 Dec 2013, Vandana Kannan wrote:
> If one mode of a internal panel has more than one refresh rate, then a reduced
> clock is found for the LFP (LVDS/eDP). This enables switching between low
> and high frequency dynamically. Moving downclock calculation to intel_panel
> so that it is comm
If one mode of a internal panel has more than one refresh rate, then a reduced
clock is found for the LFP (LVDS/eDP). This enables switching between low
and high frequency dynamically. Moving downclock calculation to intel_panel
so that it is common for LVDS and eDP.
Signed-off-by: Vandana Kannan
On Mon, 09 Dec 2013, Vandana Kannan wrote:
> If one mode of a internal panel has more than one refresh rate, then a reduced
> clock is found for the LFP (LVDS/eDP). This enables switching between low
> and high frequency dynamically. Moving downclock calculation to intel_panel
> so that it is comm
If one mode of a internal panel has more than one refresh rate, then a reduced
clock is found for the LFP (LVDS/eDP). This enables switching between low
and high frequency dynamically. Moving downclock calculation to intel_panel
so that it is common for LVDS and eDP.
Signed-off-by: Vandana Kannan
