Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

2014-09-08 Thread Thomas Richter
Am 08.09.2014 09:39, schrieb Daniel Vetter: On Fri, Sep 05, 2014 at 09:54:13PM +0300, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä 830 is very unhappy of the watermark value is too low (indicating a very high watermark in fact, ie. memory fetch will occur with an almost full FIFO).

Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

2014-09-08 Thread Daniel Vetter
On Fri, Sep 05, 2014 at 09:54:13PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > 830 is very unhappy of the watermark value is too low (indicating a very > high watermark in fact, ie. memory fetch will occur with an almost full > FIFO). Limit the watermark value to at leas

Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

2014-09-06 Thread Thomas Richter
On 06.09.2014 19:33, Ville Syrjälä wrote: The DVO 2x clock fix was missing. I posted a new version. But I think that should only affect the DVO output and not the VGA output. Anyway on my 830 nightly with those two patches is pretty damn good. I'm going to assume this is the first time in histor

Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

2014-09-06 Thread Ville Syrjälä
On Fri, Sep 05, 2014 at 09:03:11PM +0200, Thomas Richter wrote: > On 05.09.2014 20:54, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > 830 is very unhappy of the watermark value is too low (indicating a very > > high watermark in fact, ie. memory fetch will occur with an almos

Re: [Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

2014-09-05 Thread Thomas Richter
On 05.09.2014 20:54, ville.syrj...@linux.intel.com wrote: From: Ville Syrjälä 830 is very unhappy of the watermark value is too low (indicating a very high watermark in fact, ie. memory fetch will occur with an almost full FIFO). Limit the watermark value to at least 8 cache lines. That also m

[Intel-gfx] [PATCH] drm/i915: Limit the watermark to at least 8 entries on gen2/3

2014-09-05 Thread ville . syrjala
From: Ville Syrjälä 830 is very unhappy of the watermark value is too low (indicating a very high watermark in fact, ie. memory fetch will occur with an almost full FIFO). Limit the watermark value to at least 8 cache lines. That also matches the burst size we use on most platforms. BSpec seems