Re: [Intel-gfx] [PATCH] drm/i915: Fix subslice configuration on Gen9LP

2018-08-29 Thread Tvrtko Ursulin
On 23/08/2018 09:59, Tvrtko Ursulin wrote: On 22/08/2018 16:47, Lionel Landwerlin wrote: On 22/08/2018 16:27, Tvrtko Ursulin wrote: On 22/08/2018 16:22, Lionel Landwerlin wrote: On 22/08/2018 16:17, Tvrtko Ursulin wrote: On 22/08/2018 16:08, Lionel Landwerlin wrote: On 22/08/2018 15:29, T

Re: [Intel-gfx] [PATCH] drm/i915: Fix subslice configuration on Gen9LP

2018-08-23 Thread Tvrtko Ursulin
On 22/08/2018 16:47, Lionel Landwerlin wrote: On 22/08/2018 16:27, Tvrtko Ursulin wrote: On 22/08/2018 16:22, Lionel Landwerlin wrote: On 22/08/2018 16:17, Tvrtko Ursulin wrote: On 22/08/2018 16:08, Lionel Landwerlin wrote: On 22/08/2018 15:29, Tvrtko Ursulin wrote: From: Tvrtko Ursulin

Re: [Intel-gfx] [PATCH] drm/i915: Fix subslice configuration on Gen9LP

2018-08-22 Thread Lionel Landwerlin
On 22/08/2018 16:27, Tvrtko Ursulin wrote: On 22/08/2018 16:22, Lionel Landwerlin wrote: On 22/08/2018 16:17, Tvrtko Ursulin wrote: On 22/08/2018 16:08, Lionel Landwerlin wrote: On 22/08/2018 15:29, Tvrtko Ursulin wrote: From: Tvrtko Ursulin According to the documentation, when programmin

Re: [Intel-gfx] [PATCH] drm/i915: Fix subslice configuration on Gen9LP

2018-08-22 Thread Tvrtko Ursulin
On 22/08/2018 16:22, Lionel Landwerlin wrote: On 22/08/2018 16:17, Tvrtko Ursulin wrote: On 22/08/2018 16:08, Lionel Landwerlin wrote: On 22/08/2018 15:29, Tvrtko Ursulin wrote: From: Tvrtko Ursulin According to the documentation, when programming the subslice count power- gating configur

Re: [Intel-gfx] [PATCH] drm/i915: Fix subslice configuration on Gen9LP

2018-08-22 Thread Lionel Landwerlin
On 22/08/2018 16:17, Tvrtko Ursulin wrote: On 22/08/2018 16:08, Lionel Landwerlin wrote: On 22/08/2018 15:29, Tvrtko Ursulin wrote: From: Tvrtko Ursulin According to the documentation, when programming the subslice count power- gating configuration register, the value to be written into it

Re: [Intel-gfx] [PATCH] drm/i915: Fix subslice configuration on Gen9LP

2018-08-22 Thread Tvrtko Ursulin
On 22/08/2018 16:08, Lionel Landwerlin wrote: On 22/08/2018 15:29, Tvrtko Ursulin wrote: From: Tvrtko Ursulin According to the documentation, when programming the subslice count power- gating configuration register, the value to be written into it on Gen9LP should actually in the format of:

Re: [Intel-gfx] [PATCH] drm/i915: Fix subslice configuration on Gen9LP

2018-08-22 Thread Lionel Landwerlin
On 22/08/2018 15:29, Tvrtko Ursulin wrote: From: Tvrtko Ursulin According to the documentation, when programming the subslice count power- gating configuration register, the value to be written into it on Gen9LP should actually in the format of: 1 slice = 0x001 2 slices = 0x010 3 sli

Re: [Intel-gfx] [PATCH] drm/i915: Fix subslice configuration on Gen9LP

2018-08-22 Thread Tvrtko Ursulin
On 22/08/18 15:29, Tvrtko Ursulin wrote: From: Tvrtko Ursulin According to the documentation, when programming the subslice count power- gating configuration register, the value to be written into it on Gen9LP should actually in the format of: 1 slice = 0x001 2 slices = 0x010 3 slic

[Intel-gfx] [PATCH] drm/i915: Fix subslice configuration on Gen9LP

2018-08-22 Thread Tvrtko Ursulin
From: Tvrtko Ursulin According to the documentation, when programming the subslice count power- gating configuration register, the value to be written into it on Gen9LP should actually in the format of: 1 slice = 0x001 2 slices = 0x010 3 slices = 0x100 And not the popcount of the enabled