On Fri, May 05, 2017 at 09:48:08AM +0300, Jani Nikula wrote:
> On Thu, 04 May 2017, ville.syrj...@linux.intel.com wrote:
> > From: Ville Syrjälä
> >
> > Turns out our skills in decoding the CLKCFG register weren't good
> > enough. On this particular elk the answer we got was 400 MHz when
> > in re
On Thu, 04 May 2017, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä
>
> Turns out our skills in decoding the CLKCFG register weren't good
> enough. On this particular elk the answer we got was 400 MHz when
> in reality the clock was running at 266 MHz, which then caused us
> to program
From: Ville Syrjälä
Turns out our skills in decoding the CLKCFG register weren't good
enough. On this particular elk the answer we got was 400 MHz when
in reality the clock was running at 266 MHz, which then caused us
to program a bogus AUX clock divider that caused all AUX communication
to fail.
