Hi Uma,
[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v4.14-rc1 next-20170918]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/Vidya-Srinivas/drm-i915-Enable-scanline-read-
From: Uma Shankar
For gen9 platforms, dsi timings are driven from port instead of pipe
(unlike ddi). Thus, we can't rely on pipe registers to get the timing
information. Even scanline register read will not be functional.
This is causing vblank evasion logic to fail since it relies on
scanline, c
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Wednesday, September 13, 2017 11:07 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
>Subject: Re: [PATCH] drm/i915: Enable scanline read for gen9 dsi
>
>On Wed, Sep 13, 2017
On Wed, Sep 13, 2017 at 08:24:38AM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Tuesday, September 12, 2017 8:36 PM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
> >
> >Subject:
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, September 12, 2017 8:36 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
>Subject: Re: [PATCH] drm/i915: Enable scanline read for gen9 dsi
>
>On Tue, Sep 12, 2017 at
On Tue, Sep 12, 2017 at 02:21:42PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Tuesday, September 12, 2017 7:43 PM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
> >
> >Subject:
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Tuesday, September 12, 2017 7:43 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
>Subject: Re: [PATCH] drm/i915: Enable scanline read for gen9 dsi
>
>On Tue, Sep 12, 2017 at
x [mailto:intel-gfx-boun...@lists.freedesktop.org] On
> >> >Behalf Of Shankar, Uma
> >> >Sent: Tuesday, September 12, 2017 3:20 PM
> >> >To: Ville Syrjälä
> >> >Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
> >> >
> >> >Subject:
From: Uma Shankar
For gen9 platforms, dsi timings are driven from port instead of pipe
(unlike ddi). Thus, we can't rely on pipe registers to get the timing
information. Even scanline register read will not be functional.
This is causing vblank evasion logic to fail since it relies on
scanline, c
>> >To: Ville Syrjälä
>> >Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
>> >
>> >Subject: Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for
>> >gen9 dsi
>> >
>> >
>> >
>> >>-Original Message-
&g
;To: Ville Syrjälä
> >Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
> >
> >Subject: Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for gen9 dsi
> >
> >
> >
> >>-Original Message-
> >>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Shankar, Uma
>Sent: Tuesday, September 12, 2017 3:20 PM
>To: Ville Syrjälä
>Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
>Subject: Re: [Intel-gfx] [PA
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Monday, September 11, 2017 11:20 PM
>To: Shankar, Uma
>Cc: Srinivas, Vidya ;
>intel-gfx@lists.freedesktop.org;
>Kahola, Mika ; Kamath, Sunil
>; Konduru, Chandra
>Subject: Re: [PATCH] drm/i915: Enable
aturday, September 9, 2017 1:15 AM
>> >To: Ville Syrjälä
>> >Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
>> >
>> >Subject: Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for
>> >gen9 dsi
>> >
>> >On Fri, Sep 08, 2017 at 05:55:2
;To: Ville Syrjälä
> >Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
> >
> >Subject: Re: [Intel-gfx] [PATCH] drm/i915: Enable scanline read for gen9 dsi
> >
> >On Fri, Sep 08, 2017 at 05:55:24PM +0300, Ville Syrjälä wrote:
> >> On Fri, Sep 08, 2017 at 05:47:59PM +0300,
On Mon, Sep 11, 2017 at 01:04:18PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
> >Sent: Friday, September 8, 2017 8:18 PM
> >To: Srinivas, Vidya
> >Cc: intel-gfx@lists.freedesktop.org; Kahola, Mika ;
> >Kamath, Sunil
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Daniel Vetter
>Sent: Saturday, September 9, 2017 1:15 AM
>To: Ville Syrjälä
>Cc: intel-gfx@lists.freedesktop.org; Srinivas, Vidya
>Subject: Re: [Intel-gfx] [PA
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, September 8, 2017 8:18 PM
>To: Srinivas, Vidya
>Cc: intel-gfx@lists.freedesktop.org; Kahola, Mika ;
>Kamath, Sunil ; Shankar, Uma
>; Konduru, Chandra
>Subject: Re: [PATCH] drm/i915: Enable sca
On Mon, Sep 11, 2017 at 10:52:27AM +0200, Maarten Lankhorst wrote:
> Op 08-09-17 om 21:55 schreef Chris Wilson:
> > Quoting Daniel Vetter (2017-09-08 20:45:11)
> >> On Fri, Sep 08, 2017 at 05:55:24PM +0300, Ville Syrjälä wrote:
> >>> Another thought that just occurred to me: Maybe we could use thes
Op 08-09-17 om 21:55 schreef Chris Wilson:
> Quoting Daniel Vetter (2017-09-08 20:45:11)
>> On Fri, Sep 08, 2017 at 05:55:24PM +0300, Ville Syrjälä wrote:
>>> Another thought that just occurred to me: Maybe we could use these
>>> timestamps as a workaround for the DDI "scanline reads as 0 at the
>>
Quoting Daniel Vetter (2017-09-08 20:45:11)
> On Fri, Sep 08, 2017 at 05:55:24PM +0300, Ville Syrjälä wrote:
> > Another thought that just occurred to me: Maybe we could use these
> > timestamps as a workaround for the DDI "scanline reads as 0 at the
> > wrong time" problem. What we could do is che
On Fri, Sep 08, 2017 at 05:55:24PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 08, 2017 at 05:47:59PM +0300, Ville Syrjälä wrote:
> > On Fri, Sep 08, 2017 at 07:18:55PM +0530, Vidya Srinivas wrote:
> > > From: Uma Shankar
> > >
> > > For gen9 platforms, dsi timings are driven from port instead of p
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Ville Syrjälä
> Sent: perjantai 8. syyskuuta 2017 17.55
> To: Srinivas, Vidya
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH] drm/
On Fri, Sep 08, 2017 at 05:47:59PM +0300, Ville Syrjälä wrote:
> On Fri, Sep 08, 2017 at 07:18:55PM +0530, Vidya Srinivas wrote:
> > From: Uma Shankar
> >
> > For gen9 platforms, dsi timings are driven from port instead of pipe
> > (unlike ddi). Thus, we can't rely on pipe registers to get the ti
On Fri, Sep 08, 2017 at 07:18:55PM +0530, Vidya Srinivas wrote:
> From: Uma Shankar
>
> For gen9 platforms, dsi timings are driven from port instead of pipe
> (unlike ddi). Thus, we can't rely on pipe registers to get the timing
> information. Even scanline register read will not be functional.
>
From: Uma Shankar
For gen9 platforms, dsi timings are driven from port instead of pipe
(unlike ddi). Thus, we can't rely on pipe registers to get the timing
information. Even scanline register read will not be functional.
This is causing vblank evasion logic to fail since it relies on
scanline, c
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