>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Ville Syrjälä
>Sent: Monday, September 25, 2017 6:46 PM
>To: Srinivas, Vidya
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville
>Subject: Re: [Intel-gfx] [PA
On Mon, Sep 25, 2017 at 04:23:30PM +0530, Vidya Srinivas wrote:
> From: Uma Shankar
>
> For certain platforms on certain encoders, timings are driven
> from port instead of pipe. Thus, we can't rely on pipe scanline
> registers to get the timing information. Some cases scanline
> register read wi
From: Uma Shankar
For certain platforms on certain encoders, timings are driven
from port instead of pipe. Thus, we can't rely on pipe scanline
registers to get the timing information. Some cases scanline
register read will not be functional.
This is causing vblank evasion logic to fail since it
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, September 22, 2017 6:58 PM
>To: Srinivas, Vidya
>Cc: intel-gfx@lists.freedesktop.org; Kahola, Mika ;
>Kamath, Sunil ; Shankar, Uma
>; Konduru, Chandra
>Subject: Re: [PATCH] drm/i915: Enable sc
On Tue, Sep 19, 2017 at 02:50:03PM +0530, Vidya Srinivas wrote:
> From: Uma Shankar
>
> For certain platforms on certain encoders, timings are driven
> from port instead of pipe. Thus, we can't rely on pipe scanline
> registers to get the timing information. Some cases scanline
> register read ma
From: Uma Shankar
For certain platforms on certain encoders, timings are driven
from port instead of pipe. Thus, we can't rely on pipe scanline
registers to get the timing information. Some cases scanline
register read may not be functional due to certain hw issues.
This is causing vblank evasion
