Re: [Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-04 Thread Ville Syrjälä
On Wed, Apr 03, 2013 at 10:08:26PM +0200, Daniel Vetter wrote: > On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter wrote: > > So I've checked hsw bspec and the problem is that hw guys again > > changed the bits around a bit, and I think on HSW we actually want > > (0x8 << 3) instead of what's currentl

Re: [Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Ben Widawsky
On Wed, Apr 03, 2013 at 01:41:05PM -0700, Ben Widawsky wrote: > On Wed, Apr 03, 2013 at 10:08:26PM +0200, Daniel Vetter wrote: > > On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter wrote: > > > So I've checked hsw bspec and the problem is that hw guys again > > > changed the bits around a bit, and I t

Re: [Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Ben Widawsky
On Wed, Apr 03, 2013 at 10:08:26PM +0200, Daniel Vetter wrote: > On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter wrote: > > So I've checked hsw bspec and the problem is that hw guys again > > changed the bits around a bit, and I think on HSW we actually want > > (0x8 << 3) instead of what's currentl

Re: [Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Daniel Vetter
On Wed, Apr 3, 2013 at 9:33 PM, Daniel Vetter wrote: > So I've checked hsw bspec and the problem is that hw guys again > changed the bits around a bit, and I think on HSW we actually want > (0x8 << 3) instead of what's currently there. Meh, I've screwed up reading the tables, 0x3 << 3 is what we

Re: [Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Daniel Vetter
On Wed, Apr 3, 2013 at 9:17 PM, Kenneth Graunke wrote: > On 04/03/2013 11:06 AM, Ben Widawsky wrote: >> >> Apparently these ECOCHK bits changed on HSW and the behavior is not what >> we want. I've not been able to find VLV definition specifically so I'll >> assume it's the same as IVB. >> >> (Only

Re: [Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Kenneth Graunke
On 04/03/2013 11:06 AM, Ben Widawsky wrote: Apparently these ECOCHK bits changed on HSW and the behavior is not what we want. I've not been able to find VLV definition specifically so I'll assume it's the same as IVB. (Only compile tested) Reported-by: Kenneth Graunke Signed-off-by: Ben Widaws

[Intel-gfx] [PATCH] drm/i915: Don't override PPGTT cacheability on HSW

2013-04-03 Thread Ben Widawsky
Apparently these ECOCHK bits changed on HSW and the behavior is not what we want. I've not been able to find VLV definition specifically so I'll assume it's the same as IVB. (Only compile tested) Reported-by: Kenneth Graunke Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_gem_gtt.c |