Re: [Intel-gfx] [PATCH] drm/i915: Disable use of hwsp_cacheline for kernel_context

2020-02-05 Thread Chris Wilson
Quoting Mika Kuoppala (2020-02-05 14:50:58) > Chris Wilson writes: > > > Currently on execlists, we use a local hwsp for the kernel_context, > > rather than the engine's HWSP, as this is the default for execlists. > > However, seqno rollover requires allocating a new HWSP cachline, and may > > s

Re: [Intel-gfx] [PATCH] drm/i915: Disable use of hwsp_cacheline for kernel_context

2020-02-05 Thread Mika Kuoppala
Chris Wilson writes: > Currently on execlists, we use a local hwsp for the kernel_context, > rather than the engine's HWSP, as this is the default for execlists. > However, seqno rollover requires allocating a new HWSP cachline, and may s/cachline/cacheline -Mika ___

[Intel-gfx] [PATCH] drm/i915: Disable use of hwsp_cacheline for kernel_context

2020-02-05 Thread Chris Wilson
Currently on execlists, we use a local hwsp for the kernel_context, rather than the engine's HWSP, as this is the default for execlists. However, seqno rollover requires allocating a new HWSP cachline, and may require pinning a new HWSP page in the GTT. This operation requiring pinning in the GGTT

[Intel-gfx] [PATCH] drm/i915: Disable use of hwsp_cacheline for kernel_context

2020-02-04 Thread Chris Wilson
Currently on execlists, we use a local hwsp for the kernel_context, rather than the engine's HWSP, as this is the default for execlists. However, seqno rollover requires allocating a new HWSP cachline, and may require pinning a new HWSP page in the GTT. This operation requiring pinning in the GGTT